Design Procedures of W-Band Low Noise Amplifier for RFIC-5G Applications

This chapter presents a new approach of the design of a W-band Low Noise Amplifier (LNA) in a CMOS technology for narrowband and wideband applications. As a part of RFICs, Low Noise Amplifiers (LNA) play a crucial role. Being the first block in a receiver, its main responsibility is to provide enough amplification to cancel out noise from later blocks (such the filter and the mixer) while avoiding overloading the mixer with too much gain. The selection of an appropriate transistor is a critical aspect in designing an LNA stage that meets the desired performance criteria. Numerous transistor topologies are available for LNA applications. The proposed LNA utilizes input matching bandwidth extensions based on the source degeneration topology, and it is designed and optimized at a center frequency of and a supply voltage of . The obtained results exhibit a noise figure of , a power gain of , and a VSWR of 1.1. The design method for this LNA is based on a mutually beneficial trade-off between the 30 dB of available gain and the 3 dB of noise figure, which results in strong linearity and good bilateral stability, as indicated by an input third-order intercept point of -17 dBm. A detailed performance analysis is presented and discussed along this paper. With the aim of a complete and robust integration, all lumped elements and transmission lines are integrated on a silicon PCB having _r=11.7 and a dielectric loss Tan for low manufacturing costs. The LNA exhibits high linearity of at and demonstrates good stability. In future endeavors, reducing power consumption will be pursued. Consequently, the proposed model holds great promise as a suitable choice for 5G-RFIC mobile systems.